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74HC4052DB Datasheet(PDF) 15 Page - NXP Semiconductors |
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74HC4052DB Datasheet(HTML) 15 Page - NXP Semiconductors |
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15 / 27 page 
74HC_HCT4052_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 11 January 2010 15 of 27 NXP Semiconductors 74HC4052; 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer For 74HC4052: VM = 0.5 × VCC. For 74HCT4052: VM = 1.3 V. Fig 14. Turn-on and turn-off times 001aae330 tPLZ tPHZ switch OFF switch ON switch ON Vos output Vos output E, Sn inputs VM VI 0 V 90 % 10 % tPZL tPZH 50 % 50 % Definitions for test circuit; see Table 11: RT = termination resistance should be equal to the output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. RL = load resistance. S1 = Test selection switch. Fig 15. Test circuit for measuring AC performance VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aae382 VCC VCC open GND VEE VI Vos DUT CL RT RL S1 PULSE GENERATOR Vis |
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