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74HCT259D Datasheet(PDF) 2 Page - NXP Semiconductors |
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74HCT259D Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 21 page ![]() 74HC_HCT259_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 25 February 2009 2 of 21 NXP Semiconductors 74HC259; 74HCT259 8-bit addressable latch I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Ordering information 4. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC259N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT259N 74HC259D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HCT259D 74HC259DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HCT259DB 74HC259PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HCT259PW 74HC259BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm SOT763-1 74HCT259BQ Fig 1. Logic symbol Fig 2. IEC logic symbol mna573 D A0 A1 A2 MR LE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 14 15 12 11 10 9 7 6 5 4 3 2 1 13 mna572 1 9,10D Z9 G8 G10 C10 8R 13 15 14 0 1 2 3 1 2 0 DX 0 7 2 3 4 5 4 6 7 9 10 11 12 5 6 7 G |
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