74AUP2G86_4

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 04 — 29 June 2009

2 of 17

NXP Semiconductors

74AUP2G86

Low-power dual 2-input EXCLUSIVE-OR gate

3.

Ordering information

4.

Marking

[1]

The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5.

Functional diagram

Table 1.

Ordering information

Type number

Package

Temperature range

Name

Description

Version

74AUP2G86DC

−40 °C to +125 °C

VSSOP8

plastic very thin shrink small outline package; 8 leads;

body width 2.3 mm

SOT765-1

74AUP2G86GT

−40 °C to +125 °C

XSON8

plastic extremely thin small outline package; no leads;

8 terminals; body 1

× 1.95 × 0.5 mm

SOT833-1

74AUP2G86GD

−40 °C to +125 °C

XSON8U

plastic extremely thin small outline package; no leads;

8 terminals; UTLP based; body 3

× 2 × 0.5 mm

SOT996-2

74AUP2G86GM

−40 °C to +125 °C

XQFN8U

plastic extremely thin quad flat package; no leads;

8 terminals; UTLP based; body 1.6

× 1.6 × 0.5 mm

SOT902-1

Table 2.

Marking codes

Type number

Marking code[1]

74AUP2G86DC

p86

74AUP2G86GT

p86

74AUP2G86GT

p86

74AUP2G86GM

p86

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

001aah760

1A

1B

1Y

2A

2B

2Y

001aah761

= 1

= 1

Fig 3.

Logic diagram (one gate)

mna040

Y

B

A