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74AUP2G02DC Datasheet(PDF) 10 Page - NXP Semiconductors |
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74AUP2G02DC Datasheet(HTML) 10 Page - NXP Semiconductors |
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10 / 17 page  74AUP2G02_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 11 December 2008 10 of 17 NXP Semiconductors 74AUP2G02 Low-power dual 2-input NOR gate [1] For measuring enable and disable times RL = 5 kΩ. For measuring propagation delays, set-up and hold times and pulse width RL = 1 MΩ. Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Load circuitry for switching times 001aac521 DUT RT VI VO VEXT VCC RL 5 k Ω CL G Table 10. Test data Supply voltage Load VEXT VCC CL RL[1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k Ω or 1 MΩ open GND 2 × VCC |
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