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74AUP1G386GW Datasheet(PDF) 10 Page - NXP Semiconductors

Part # 74AUP1G386GW
Description  Low-power 3-input EXCLUSIVE-OR gate
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

74AUP1G386GW Datasheet(HTML) 10 Page - NXP Semiconductors

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74AUP1G386_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 2 July 2009
10 of 16
NXP Semiconductors
74AUP1G386
Low-power 3-input EXCLUSIVE-OR gate
[1]
For measuring enable and disable times RL =5kΩ, for measuring propagation delays, setup and hold times and pulse width RL =1MΩ.
Table 9.
Measurement points
Supply voltage
Output
Input
VCC
VM
VM
VI
tr = tf
0.8 V to 3.6 V
0.5
× V
CC
0.5
× V
CC
VCC
≤ 3.0 ns
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8.
Load circuitry for switching times
001aac521
DUT
RT
VI
VO
VEXT
VCC
RL
5 k
Ω
CL
G
Table 10.
Test data
Supply voltage
Load
VEXT
VCC
CL
RL[1]
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF 5 k
Ω or 1 MΩ
open
GND
2
× VCC


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