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74AUP1G98GF Datasheet(PDF) 4 Page - NXP Semiconductors |
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74AUP1G98GF Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 19 page 74AUP1G98_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 29 June 2009 4 of 19 NXP Semiconductors 74AUP1G98 Low-power configurable multiple function gate 7.1 Logic configurations Table 5. Function selection table Logic function Figure 2-input MUX with inverted output see Figure 5 2-input NAND see Figure 6 2-input NOR with one input inverted see Figure 7 2-input AND with one input inverted see Figure 7 2-input NAND with one input inverted see Figure 8 2-input OR with one input inverted see Figure 8 2-input NOR see Figure 9 Buffer see Figure 10 Inverter see Figure 11 Fig 5. 2-input MUX with inverted output Fig 6. 2-input NAND gate 001aad991 B Y C VCC A C 1 2 3 6 5 4 B A Y 001aad992 Y C VCC A C 1 2 3 6 5 4 A Y Fig 7. 2-input AND gate with input A inverted or 2-input NOR gate with inverted C input Fig 8. 2-input OR gate with input B inverted or 2-input NAND gate with input C inverted 001aad993 Y C VCC A C A C 1 2 3 6 5 4 A Y Y 001aad994 Y C VCC B C B C 1 2 3 6 5 4 B Y Y Fig 9. 2-input NOR gate Fig 10. Buffer 001aad995 Y C VCC B C 1 2 3 6 5 4 B Y 001aad996 Y C VCC C 1 2 3 6 5 4 Y |
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