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74ALVC373BQ Datasheet(PDF) 11 Page - NXP Semiconductors |
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74ALVC373BQ Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 17 page 74ALVC373_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 18 October 2007 11 of 17 NXP Semiconductors 74ALVC373 Octal D-type transparent latch; 3-state Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 12. Test circuitry for switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aae331 VEXT VCC VI VO DUT CL RT RL RL G Table 9. Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 k Ω open 2 × V CC GND 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × V CC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6 V GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6 V GND |
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