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74ABT841D Datasheet(PDF) 7 Page - NXP Semiconductors |
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74ABT841D Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 15 page 74ABT841_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 25 March 2010 7 of 15 NXP Semiconductors 74ABT841 10-bit bus interface latch; 3-state 11. Waveforms VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Propagation delay for data to output 001aae916 VM VM tPLH tPHL VM VI VM Dn Qn VOH VOL GND VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Propagation delay, latch enable input to output and enable pulse width 001aae914 tPHL tPLH tWH VM VM VM VM VM LE GND Qn tWL VI VOH VOL VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. 3-state output (Qn) enable and disable times 001aal299 tPLZ tPHZ outputs disabled outputs enabled VOH − 0.3 V VOL + 0.3 V outputs enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH OE input VI VOL VOH 3.5 V VM GND GND tPZL tPZH VM VM |
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