MX7705_10 datasheet(23/33 Pages) MAXIM

Part #	MX7705

Description	16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC

Download	33 Pages

Scroll/Zoom	100%

Manufacturer	MAXIM [Maxim Integrated Products]

Direct Link	https://www.maximintegrated.com/en.html

Logo

23 / 33 page

ZERO: (Default = 0) Zero Bit. This is a read-only bit.

Values written to this bit are ignored.

CLKDIS: (Default = 0) Clock-Disable Bit. Set CLKDIS =

1 to disable the clock when using a crystal or resonator

across CLKIN and CLKOUT. Set CLKDIS = 1 to disable

CLKOUT when using a CMOS clock source at CLKIN.

CLKOUT is held low during clock disable to save

power. Set CLKDIS = 0 to allow other devices to use

the output signal on CLKOUT as a clock source and/or

to enable the external oscillator.

CLKDIV: (Default = 0) Clock-Divider Control Bit. The

MX7705 has an internal clock divider. Set this bit to 1 to

divide the input clock by two. When this bit is set to 0, the

MX7705 operates at the external oscillator frequency.

CLK: (Default = 1) Clock Bit. Set CLK = 1 for fCLKIN =

2.4576MHz with CLKDIV = 0, or 4.9152MHz with

CLKDIV = 1.

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

______________________________________________________________________________________

23

Table 6. Communications Register

FIRST BIT (MSB)

(LSB)

FUNCTION

COMMUNICATION

START/DATA READY

REGISTER SELECT

READ/WRITE

SELECT

POWER-DOWN

MODE

CHANNEL SELECT

Name

0/

DRDY

RS2

RS1

RS0

R/

W

PD

CH1

CH0

Defaults

0

Table 7. Register Selection

RS2

RS1

RS0

REGISTER

POWER-ON RESET STATUS

REGISTER SIZE (BITS)

0

Communications Register

0x00

8

0

1

Setup Register

0x01

8

0

1

0

Clock Register

0x05

8

0

1

Data Register

N/A

16

1

0

Test Register*

N/A

8

1

0

1

No Operation

—

1

0

Offset Register

0x1F 40 00

24

1

Gain Register

0x57 61 AB

24

Table 8. Channel Selection

CH1

CH0

AIN+

AIN-

OFFSET/GAIN

REGISTER PAIR

0

AIN1+

AIN1-

0

1

AIN2+

AIN2-

1

0

AIN1-

0

1

AIN1-

AIN2-

2

*

The test register is used for factory testing only.

Table 9. Setup Register

FIRST BIT (MSB)

(LSB)

FUNCTION

MODE CONTROL

PGA GAIN CONTROL

BIPOLAR/UNIPOLAR

MODE

BUFFER ENABLE

FSYNC

Name

MD1

MD0

G2

G1

G0

B/U

BUF

FSYNC

Defaults

0

1

Similar Part No. - MX7705_10

Manufacturer	Part #	Datasheet	Description
Maxim Integrated Produc...	MX7705EPE	664Kb / 34P	16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC Rev 0; 10/03
	MX7705EPE	405Kb / 33P	16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC Rev 3; 6/09
	MX7705EPE++	465Kb / 33P	16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC 2015
	MX7705EUE	664Kb / 34P	16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC Rev 0; 10/03
	MX7705EUE	405Kb / 33P	16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC Rev 3; 6/09

More results

Similar Description - MX7705_10

Manufacturer	Part #	Datasheet	Description
Maxim Integrated Produc...	MX7705	664Kb / 34P	16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC Rev 0; 10/03
	MX7705	465Kb / 33P	16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC 2015
	MX7705	405Kb / 33P	16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC Rev 3; 6/09
Analog Devices	AD7171	284Kb / 16P	16-Bit Low Power Sigma-Delta ADC REV. 0
	AD7171	313Kb / 17P	16-Bit, Low Power, Sigma-Delta ADC
	AD7787	307Kb / 20P	Low Power, 2-Channel 24-Bit Sigma-Delta ADC REV. A
	AD7787	326Kb / 20P	Low Power, 2-Channel 24-Bit Sigma-Delta ADC REV. 0
	AD7787	307Kb / 20P	Low Power, 2-Channel 24-Bit Sigma-Delta ADC REV. A
	AD7787	362Kb / 21P	Low Power, 2-Channel 24-Bit Sigma-Delta ADC
	AD7790	299Kb / 20P	Low Power, 16-Bit Buffered Sigma-Delta ADC REV. 0

More results

MX7705 Datasheet(PDF) 23 Page - Maxim Integrated Products

MX7705 Datasheet(HTML) 23 Page - Maxim Integrated Products

Similar Part No. - MX7705_10

Similar Description - MX7705_10

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Datasheet Download

Link URL