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MX7705 Datasheet(PDF) 18 Page - Maxim Integrated Products

Part No. MX7705
Description  16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MX7705 Datasheet(HTML) 18 Page - Maxim Integrated Products

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To minimize gain errors in unbuffered mode, select a
source impedance less than the maximum values
shown in Figures 2 and 3. These are the maximum
external resistance/capacitance combinations allowed
before gain errors greater than 1 LSB are introduced in
unbuffered mode.
Enable the internal input buffer for a high source imped-
ance. This isolates the inputs from the sampling capaci-
tor and reduces the sampling-related gain error. When
using the internal buffer, limit the absolute input voltage
range to (VGND + 50mV) to (VDD - 1.5V). Set gain and
common-mode voltage range properly to minimize lin-
earity errors.
Input Voltage Range
In unbuffered mode, the absolute analog input voltage
range is from (GND - 30mV) to (VDD + 30mV) (see the
Electrical Characteristics). In buffered mode, the ana-
log input voltage range is reduced to (GND + 50mV) to
(VDD - 1.5V). In both buffered and unbuffered modes,
the differential analog input range (VAIN+ - VAIN-)
decreases at higher gains (see the
Programmable-Gain
Amplifier and the Unipolar and Bipolar Modes sections).
Reference
The MX7705 provides differential inputs, REF+ and REF-,
for an external reference voltage. Connect the external
reference directly across REF+ and REF- to obtain the
differential reference voltage, VREF. The common-mode
voltage range for VREF+ and VREF- is between GND
and VDD. For specified operation, the nominal voltage,
VREF (VREF+ - VREF-), is 2.5V for VDD = 4.75V to 5.25V
and 1.225V for VDD = 2.7V to 3.6V.
The MX7705 samples REF+ and REF- at fCLKIN / 64
(CLKDIV = 0) or fCLKIN / 128 (CLKDIV = 1) with an
internal 10pF (typ for gain = 1) sampling capacitor in
series with a 7k
Ω (typ) switch on-resistance.
Programmable-Gain Amplifier
A PGA provides selectable levels of gain: 1, 2, 4, 8, 16,
32, 64, and 128. Bits G0, G1, and G2 in the setup reg-
ister control the gain (Table 9). As the gain increases,
the value of the input sampling capacitor, CSAMP, also
increases (Table 5). The dynamic load presented to the
analog inputs increases with clock frequency and gain
in unbuffered mode (see the
Input Buffers section and
Figure 1).
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
18
______________________________________________________________________________________
HIGH
IMPEDANCE
RSW (7k
Ω TYP)
CTOTAL(7pF TYP FOR GAIN = 1)
AIN(+)
AIN(-)
VBIAS
CTOTAL = CSAMP + CSTRAY
Figure 1. Unbuffered Analog Input Structure
0.1
1
10
100
1
10
100
1000
10,000
EXTERNAL CAPACITANCE (pF)
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8 TO 128
Figure 2. Maximum External Resistance vs. Maximum External
Capacitance for Unbuffered Mode (1MHz)
0.1
1
10
100
1
10
100
1000
10,000
EXTERNAL CAPACITANCE (pF)
GAIN = 2
GAIN = 4
GAIN = 8 TO 128
GAIN = 1
Figure 3. Maximum External Resistance vs. Maximum External
Capacitance for Unbuffered Mode (2.4576MHz)


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