Real-Time Clocks

8

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Pin Description

PIN

SO,

PDIP

EDIP

PLCC

TQFP

NAME

FUNCTION

1

1

2

29

MOT

Motorola or Intel Bus Timing Selector. This pin selects one of two bus types. When

left disconnected, Intel bus timing is selected. The pin has an internal pulldown

resistor.

2—

3

30

X1

3—

4

31

X2

Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator

circuitry is designed for operation with a crystal having a 6pF specified load

connected to an external 32.768kHz oscillator. The output of the internal oscillator,

pin X2, is left unconnected if an external oscillator is connected to pin X1.

4–11

4–11

5–10,

12, 14

1, 2, 3,

5, 7, 8,

9, 11

AD0–

AD7

Multiplexed, Bidirectional Address/Data Bus. The addresses are presented during

the first portion of the bus cycle and latched into the device by the falling edge of

AS. Write data is latched by the falling edge of DS (Motorola timing) or the rising

edge of R/W (Intel timing). In a read cycle, the device outputs data during the

latter portion of DS (DS and R/W high for Motorola timing, DS low and R/W high for

Intel timing). The read cycle is terminated and the bus returns to a high-

impedance state as DS transitions low in the case of Motorola timing or as DS

transitions high in the case of Intel timing.

12, 16

12

15, 20

12, 17

GND

Ground

13

13

16

13

CS

Active-Low Chip-Select Input. The chip-select signal must be asserted low for a

bus cycle in the device to be accessed. CS must be kept in the active state during

DS and AS for Motorola timing and during DS and R/W for Intel timing. Bus cycles

that take place without asserting CS will latch addresses, but no access occurs.

CS input. This action protects the RTC data and the RAM data during power

outages.

14

14

17

14

AS

Address Strobe Input. A positive-going address-strobe pulse serves to

demultiplex the bus. The falling edge of AS causes the address to be latched

within the device. The next rising edge that occurs on the AS bus clears the

address regardless of whether CS is asserted. An address strobe must

immediately precede each write or read access. If a write or read is performed

with CS deasserted, another address strobe must be performed prior to a read or

write access with CS asserted.

15

15

19

16

R/W

Read/Write Input. The R/W pin has two modes of operation. When the MOT pin is

current cycle is a read or write. A read cycle is indicated with a high level on R/W

while DS is high. A write cycle is indicated when R/W is low during DS. When the

MOT pin is connected to GND for Intel timing, the R/W signal is an active-low

signal. In this mode, the R/W pin operates in a similar fashion as the write-enable

signal (WE) on generic RAMs. Data are latched on the rising edge of the signal.