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ADuM3220ARZ Datasheet(PDF) 4 Page - Analog Devices |
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ADuM3220ARZ Datasheet(HTML) 4 Page - Analog Devices |
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4 / 16 page  ADuM3220 Rev. 0 | Page 4 of 16 ELECTRICAL CHARACTERISTICS—3.3 V OPERATION All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/ maximum specifications apply over TJ = −40°C to 125°C. All typical specifications are at TJ = 25°C, VDD1 = 3.3 V, VDD2 = 10 V. Switching specifications are tested with CMOS signal levels. Table 2. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, Two Channels, Quiescent IDDI(Q) 0.7 1.0 mA Output Supply Current, Two Channels, Quiescent IDDO(Q) 4.7 10 mA Total Supply Current, Two Channels1 DC to 1 MHz VDD1 Supply Current IDD1(Q) 0.8 1.0 mA DC to 1 MHz logic signal frequency VDD2 Supply Current IDD2(Q) 11 17 mA DC to 1 MHz logic signal frequency Input Currents IIA, IIB −10 +0.01 +10 μA 0 ≤ VIA, VIB ≤ VDD1 Logic High Input Threshold VIH 0.7 × VDD1 V Logic Low Input Threshold VIL 0.3 × VDD1 V Logic High Output Voltages VOAH, VOAH VDD2 − 0.1 VDD2 V IOx = −20 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL 0.0 0.15 V IOx = +20 mA, VIx = VIxL Undervoltage Lockout, VDD2 Supply Positive Going Threshold VDD2UV+ 3.7 4.1 4.4 V Negative Going Threshold VDD2UV− 3.2 3.7 4.1 V Hysteresis VDD2UVH 0.4 V Output Short-Circuit Pulsed Current2 IOA(SC), IOB(SC) 2.0 4.0 A VDD2 = 10 V SWITCHING SPECIFICATIONS Pulse Width3 PW 100 ns CL = 2 nF, VDD2 = 10 V Data Rate4 1 MHz CL = 2 nF, VDD2 = 10 V Propagation Delay5 tDLH, tDHL 36 48 62 ns CL = 2 nF, VDD2 = 10 V; see Figure 17 tDLH, tDHL 37 53 72 ns CL = 2 nF, VDD2 = 4.5 V; see Figure 17 Propagation Delay Skew6 tPSK 12 ns CL = 2 nF, VDD2 = 10 V; see Figure 17 Channel-to-Channel Matching7 tPSKCD 1 5 ns CL = 2 nF, VDD2 = 10 V; see Figure 17 tPSKCD 1 7 ns CL = 2 nF, VDD2 = 4.5 V; see Figure 17 Output Rise/Fall Time (10% to 90%) tR/tF 14 20 25 ns CL = 2 nF, VDD2 = 10 V; see Figure 17 tR/tF 14 22 28 ns CL = 2 nF, VDD2 = 4.5 V; see Figure 17 Dynamic Input Supply Current per Channel IDDI(D) 0.025 mA/Mbps VDD2 = 10 V Dynamic Output Supply Current per Channel IDDO(D) 1.5 mA/Mbps VDD2 = 10 V Refresh Rate fr 1.1 Mbps 1 The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See Figure 8 and Figure 9 for total VDD1 and VDD2 supply currents as a function of data rate. Power Consumption 2Short-circuit duration less than 1 μs. Average power must conform to the limit shown under the . .Absolute Maximum Ratings 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 TDLH propagation delay is measured from the 90% level of the rising edge of the VIx signal to the 10% level of the rising edge of the VOx signal. tDHL propagation delay is measured from the 10% level of the falling edge of the VIx signal to the 90% level of the falling edge of the VOx signal. See Figure 17 for waveforms of propagation delay parameters. 6 tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. See Figure 17 for waveforms of propagation delay parameters. 7 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. |
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