ADRF6601ACPZ-R7 datasheet(4/24 Pages) AD

Part #	ADRF6601ACPZ-R7

Description	750 MHz to 1160 MHz Rx Mixer with Integrated Fractional-N PLL and VCO

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ADRF6601

Rev. 0 | Page 4 of 24

SYNTHESIZER/PLL SPECIFICATIONS

VCCx = 5 V; ambient temperature (TA) = 25°C; fREF = 153.6 MHz; fREF power = 4 dBm; fPFD = 38.4 MHz; high-side LO injection;

fIF = 140 MHz; IIP3 optimized using CDAC = 0x1 and IP3SET = 3.3 V, unless otherwise noted.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

SYNTHESIZER SPECIFICATIONS

Synthesizer specifications referenced to 1× LO

Frequency Range

Internally generated LO

750

1160

MHz

Figure of Merit1

fREF power = 0 dBm

−221.4

dBc/Hz

Reference Spurs

fREF = 153.6 MHz

fREF/4

−107

dBc

fREF/2

−107

dBc

fREF

−84

dBc

> fREF

−88

dBc

PHASE NOISE

fLO = 750 MHz to 1160 MHz, fPFD = 38.4 MHz

1 kHz to 10 kHz offset

−102

dBc/Hz

100 kHz offset

−108.6

dBc/Hz

500 kHz offset

−127

dBc/Hz

1 MHz offset

−135

dBc/Hz

5 MHz offset

−147

dBc/Hz

10 MHz offset

−151

dBc/Hz

20 MHz offset

−153

dBc/Hz

Integrated Phase Noise

1 kHz to 40 MHz integration bandwidth

0.13

°rms

PFD Frequency

20

40

MHz

REFERENCE CHARACTERISTICS

REF_IN, MUXOUT pins

REF_IN Input Frequency

12

160

MHz

REF_IN Input Capacitance

4

pF

MUXOUT Output Level

VOL (lock detect output selected)

0.25

V

VOH (lock detect output selected)

2.7

V

MUXOUT Duty Cycle

50

%

CHARGE PUMP

Pump Current

Programmable to 250 μA, 500 μA, 750 μA, 1 mA

500

μA

Output Compliance Range

1

2.8

V

1 The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10log10(fPFD) – 20log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 80 MHz,

fREF power = 10 dBm (500 V/μs slew rate) with a 40 MHz fPFD. The FOM was computed at 50 kHz offset.

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