X88C64

10

RD Controlled Read Cycle

Symbol

Parameter

Min.

Max.

Units

ALE Pulse Width

80

ns

Address Setup Time

20

ns

Address Hold Time

30

ns

RD Read Access Time

120

ns

Data Hold Time

0

ns

Chip Enable Setup Time

7

ns

RD Pulse Width

150

ns

RD Setup Time

30

ns

RD Hold Time

20

ns

RD Disable to Output in High Z

50

ns

RD to Output in Low Z

0

ns

3867 PGM T10

RD Controlled Read Timing Diagram

Note:

(6) This parameter is periodically sampled and not 100% tested.

3867 FHD F06

ALE

A/D0–A/D7

A8–A12

RD

AIN

tRLDV

DOUT

tRDH

tRDH

tLHLL

tAVLL

tLLAX

tRDS

PWRL

ADDRESS

CE

tRLDX

tRHDZ

tRHDX

tELLL