X88C75PI datasheet(11/27 Pages) XICOR

Part #	X88C75PI

Description	Port Expander and E2 Memory

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Manufacturer	XICOR [Xicor Inc.]

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X88C75 SLIC® E2

11

PRINCIPLES OF OPERATION

I/O Port Operation

The expansion ports are accessible to the software

using their assigned memory mapped addresses. Each

port occupies two addresses in the SFR plane, the Port

Data Register and Port Pin Register. These registers

and their location in the 1K-byte register memory space

is shown on page 7.

The ports can be configured as either inputs or outputs,

the DIRA and DIRB bits in the configuration register are

used to select between the modes. The input signal on

the strobe pin, when the corresponding port is config-

ured as an input, is fed to the clock input of the port latch.

These are transparent latches and the trailing edge of

the strobe pulse is used to latch the data present on the

input pins. The strobe signal polarity is configurable

using the STPA and STPB bits in the configuration

register.

Writing to the port data register of an output port will

generate a pulse of fixed duration on its strobe pin. The

data also simultaneously arrives at the port output pins.

The latched data stays there until new data is written to

the port data register. The strobe pulse shape is con-

trolled by the state of the STPA and STPB bits in the

configuration register. A “1” forces the valid transition on

the corresponding strobe pin as active HIGH (

),

and a “0” sets it to active LOW (

).

When an external strobe signal is applied to an input

port, the latching of input data is followed by the setting

of the interrupt flags. The INTA and INTB interrupt flags

are used by ports A and B respectively, and are set along

with the INT interrupt flag at the end of strobe pulse input.

External interrupt (

IRQ) is generated if the interrupt

enable flags (ENA and ENB) are set by the software.

The former enables the port A interrupt and the latter

enables the port B interrupt.

The port output drivers can be either CMOS or open-

drain. The wire-OR bits (AWO, BWO) in the configura-

tion register are used to make the selection. When the

bits are “0” the CMOS drivers are enabled. Setting these

bits will enable the open-drain output drivers. Small pull-

up resistors should be used on the pins of open-drain

ports.

INTERNAL DATA BUS

I/O

PORT

OUTPUT

INPUT

LATCH FOR

I/O PIN

PORT WRITE

(PORT OUTPUT)

STROBE (PORT INPUT)

2887 ILL F16.1

PORT READ

(PORT INPUT)

PIN READ

(PORT IN OR OUTPUT)

Figure 12. Block Diagram of the I/O Ports

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