X88257

8

RD Controlled Read Cycle

Symbol

Parameter

Min.

Max.

Units

ALE Pulse Width

80

ns

Address Setup Time

20

ns

Address Hold Time

30

ns

RD Read Access Time

120

ns

Data Hold Time

0

ns

Chip Enable Setup Time

7

ns

RD Pulse Width

150

ns

RD Setup Time

30

ns

RD Hold Time

20

ns

RD Disable to Output in High Z

50

ns

RD to Output in Low Z

0

ns

6509 PGM T10

RD Controlled Read Timing Diagram

ALE

A/D0–A/D7

A8–A14

RD

AIN

tRLDV

DOUT

tRDH

tRDH

tLHLL

tAVLL

tLLAX

tRDS

PWRL

ADDRESS

CE

tRLDX

tRHDZ

tRHDX

tELLL

6509 ILL F06.1

Note:

(6) This parameter is periodically sampled and not 100% tested.

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

SYMBOL TABLE