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X24F016P-5 Datasheet(PDF) 7 Page - Xicor Inc. |
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X24F016P-5 Datasheet(HTML) 7 Page - Xicor Inc. |
7 / 18 page X24F064/032/016 7 Current Address Read Internally, the X24F064/032/016 contains an ad- dress counter that maintains the address of the last byte read, incremented by one byte. Therefore, if the last read was from address n, the next read opera- tion accesses data from address n + 1. Upon receipt of the slave address with the R/W set HIGH, the X24F064/032/016 issues an acknowledge and trans- mits the eight-bit word. The read operation is termi- nated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 6 for the sequence of address, acknowl- edge and data transfer. Random Read Random read operations allow the master to access any memory location in a random manner. Prior to is- suing the slave address with the R/W bit set HIGH, the master must first perform a “dummy” write operation. The master issues the start condition, and the slave ad- dress with the R/W bit set LOW, followed by the byte address it is to read. After the byte address acknowl- edge, the master immediately reissues the start condi- tion and the slave address with the R/W bit set HIGH. This will be followed by an acknowledge from the X24F064/032/016 and then by the eight-bit byte. The read operation is terminated by the master; by not re- sponding with an acknowledge and by issuing a stop condition. Refer to Figure 7 for the address, acknowl- edge and data transfer sequence. Figure 7. Random Read BUS ACTIVITY: MASTER SDA LINE BUS ACTIVITY: X24F016/032/064 S T A R T SLAVE ADDRESS S A C K 6686 ILL F12.3 S T A R T S BYTE ADDRESS n A C K SLAVE ADDRESS DATA n A C K S T O P P Figure 6. Current Address Read BUS ACTIVITY: MASTER SDA LINE BUS ACTIVITY: X24F016/032/064 S T A R T SLAVE ADDRESS S S T O P P A C K DATA 6686 ILL F11.1 |
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