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X24F128PE Datasheet(PDF) 5 Page - Xicor Inc. |
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X24F128PE Datasheet(HTML) 5 Page - Xicor Inc. |
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5 / 16 page  X24F128 5 Figure 4. Device Addressing 1 S1 S0 R/W DEVICE SELECT 0 1 0 S2 0 A10 A9 A8 0 A13 HIGH ORDER ADDRESS A12 A11 DEVICE TYPE IDENTIFIER SLAVE ADDRESS BYTE D7 D2 D1 D6 D5 D4 D3 DATA BYTE ADDRESS BYTE 1 A2 A1 A0 A5 LOW ORDER ADDRESS A4 A3 ADDRESS BYTE 0 A7 A6 D0 7012 ILL F06.1 DEVICE ADDRESSING Following a start condition, the master must output the address of the slave it is accessing. The first four bits of the Slave Address Byte are the device type identifier bits. These must equal “1010”. The next 3 bits are the device select bits S0, S1, and S2. This allows up to 8 devices to share a single bus. These bits are compared to the S0, S1, and S2 device select input pins. The last bit of the Slave Address Byte defines the operation to be performed. When the R/W bit is a one, then a read operation is selected. When it is zero then a program operation is selected. Refer to figure 4. After loading the Slave Address Byte from the SDA bus, the device compares the device type bits with the value “1010” and the device select bits with the status of the device select input pins. If the compare is not successful, no acknowledge is output during the ninth clock cycle and the device returns to the standby mode. The byte address is either supplied by the master or obtained from an internal counter, depending on the operation. When required, the master must supply the two Address Bytes as shown in figure 4. The internal organization of the E2 array is 512 sectors by 32 bytes per sector. The sector address is partially contained in the Address Byte 1 and partially in bits 7 through 5 of the Address Byte 0. The specific byte address is contained in bits 4 through 0 of the Address Byte 0. Refer to figure 4. |
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