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X24012S-2.7 Datasheet(PDF) 5 Page - Xicor Inc. |
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X24012S-2.7 Datasheet(HTML) 5 Page - Xicor Inc. |
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5 / 14 page  X24012 5 BUS ACTIVITY: MASTER SDA LINE BUS ACTIVITY: X24012 S T A R T SLAVE ADDRESS S S T O P P A C K A C K A C K A C K A C K WORD ADDRESS n DATA n DATA n–1 DATA n+3 NOTE: In this example n = xxxx 0000 (B); x = 1 or 0 BUS ACTIVITY: MASTER SDA LINE BUS ACTIVITY: X24012 S T A R T SLAVE ADDRESS S S T O P P A C K A C K A C K WORD ADDRESS DATA DEVICE ADDRESSING Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see Figure 4). For the X24012 this is fixed as 1010[B]. Following the start condition, the X24012 monitors the SDA bus comparing the slave address being transmit- ted with its slave address (device type and state of A0, A1 and A2 inputs). Upon a correct compare the X24012 outputs an acknowledge on the SDA line. Depending on the state of the R/ W bit, the X24012 will execute a read or write operation. WRITE OPERATIONS Byte Write For a write operation, the X24012 requires a second address field. This address field is the word address, comprised of eight bits, providing access to any one of the 128 words of memory. Note: the most significant bit is a don’t care. Upon receipt of the word address the X24012 responds with an acknowledge, and awaits the next eight bits of data, again responding with an ac- knowledge. The master then terminates the transfer by generating a stop condition, at which time the X24012 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24012 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence. Figure 4. Slave Address The next three significant bits address a particular device. A system could have up to eight X24012 devices on the bus (see Figure 10). The eight addresses are defined by the state of the A0, A1 and A2 inputs. The last bit of the slave address defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operation is selected. Figure 5. Byte Write Figure 6. Page Write 1 0 1 0 A2 A1 A0 R/W DEVICE TYPE IDENTIFIER DEVICE ADDRESS 3847 FHD F08 3847 FHD F09 3847 FHD F10 BUS ACTIVITY: MASTER SDA LINE BUS ACTIVITY: X24012 BUS ACTIVITY: MASTER SDA LINE BUS ACTIVITY: X24012 |
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