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X24042S8I-2.7 Datasheet(PDF) 11 Page - Xicor Inc. |
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X24042S8I-2.7 Datasheet(HTML) 11 Page - Xicor Inc. |
11 / 15 page X24042 11 SCL SDA 8th BIT WORD n ACK tWR STOP CONDITION START CONDITION X24042 ADDRESS WRITE CYCLE LIMITS Symbol Parameter Min. Typ.(5) Max. Units tWR(6) Write Cycle Time 5 10 ms 3849 PGM T09 The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24042 bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. 3849 FHD F05 Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V). (6) tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device requires to perform the internal write operation. Write Cycle Timing Guidelines for Calculating Typical Values of Bus Pull-Up Resistors SYMBOL TABLE 3849 FHD F17 120 100 80 40 60 20 20 40 60 80 100 120 0 0 BUS CAPACITANCE (pF) MIN. RESISTANCE MAX. RESISTANCE RMAX = CBUS tRMAX RMIN = IOL MIN VCC MAX =1.8K Ω Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance OUTPUTS INPUTS WAVEFORM |
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