X24001

5

Read Operation

The byte read operation is initiated with a start condition.

The start condition is followed by an eight-bit control byte

which consists of a two-bit read command (1,0), four

address bits, and two “don’t care” bits. After receipt of

the control byte, the X24001 will enter the read mode

and transfer data into the shift register from the array.

This data is shifted out of the device on the next eight

SCL clocks. At the end of the read, all counters are reset

and the X24001 will enter the standby mode. As with a

write, the read operation can be interrupted by a start or

stop condition while the command or address is being

clocked in. While clocking data out, starts or stops

cannot be generated.

During the second don’t care clock cycle, starts and

stops are ignored. The master must free the bus prior to

the end of this clock cycle to allow the X24001 to begin

outputting data (Figures 4 and 5).

3830 FHD F07

Figure 4. Read Sequence

3830 FHD F06

Figure 5. Read Cycle Timing

6781

SDA IN

SCK

SDA OUT

A0

XX

XX

D7

D6

START

1

0

A3 A2 A1 A0 XX XX D7 D6 D5 D4 D3 D2 D1 D0

SYMBOL TABLE

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance