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X1227 Datasheet(PDF) 6 Page - Xicor Inc.

Part No. X1227
Description  Real Time Clock/Calendar/CPU Supervisor with EEPROM
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Maker  XICOR [Xicor Inc.]
Homepage  http://www.xicor.com
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X1227 Datasheet(HTML) 6 Page - Xicor Inc.

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X1227
REV 1.1.20 1/13/03
Characteristics subject to change without notice.
6 of 28
www.xicor.com
until the part powers up again. Writes to WEL bit do
not cause a nonvolatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a ‘1’ after a total power failure. This is
a read only bit that is set by hardware (X1227 inter-
nally) when the device powers up after having lost all
power to the device. The bit is set regardless of
whether VCC or VBACK is applied first. The loss of only
one of the supplies does not result in setting the RTCF
bit. The first valid write to the RTC after a complete
power failure (writing one byte is sufficient) resets the
RTCF bit to ‘0’.
Unused Bits:
This device does not use bits 3 or 4 in the SR, but
must have a zero in these bit positions. The Data Byte
output during a SR read will contain zeros in these bit
locations.
CONTROL REGISTERS
The Control Bits and Registers, described under this
section, are nonvolatile.
Block Protect Bits—BP2, BP1, BP0
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight segments
of the array. The partitions are described in Table 3 .
Table 3. Block Protect Bits
Watchdog Timer Control Bits—WD1, WD0
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 4 for options.
Table 4. Watchdog Timer Time-Out Options
ON-CHIP OSCILLATOR COMPENSATION
Digital Trimming Register (DTR) — DTR2, DTR1
and DTR0 (Non-Volatile)
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented
by using three bits above.
Table 5. Digital Trimming Registers
Protected Addresses
X1227
Array Lock
0
0
0
None (Default)
None
001
180h – 1FFh
Upper 1/4
010
100h – 1FFh
Upper 1/2
011
000h – 1FFh
Full Array
100
000h – 03Fh
First Page
101
000h – 07Fh
First 2 pgs
110
000h – 0FFh
First 4 pgs
111
000h – 1FFh
First 8 pgs
WD1 WD0
Watchdog Time-Out Period
0
0
1.75 seconds (Factory Default)
0
1
750 milliseconds
1
0
250 milliseconds
1
1
Disabled
DTR Register
Estimated frequency
PPM
DTR2
DTR1
DTR0
0
0
0
0 (Default)
0
1
0
+10
0
0
1
+20
0
1
1
+30
10
0
0
1
1
0
-10
1
0
1
-20
1
1
1
-30


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