Rev 1.1a

Copyright

© 1994

11861 Western Avenue

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∞ Garden Grove, CA 92841

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(714) 898-8121

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SG1526/SG2526/SG3526

APPLICATION INFORMATION

VOLTAGE REFERENCE

The reference regulator of the SG1526 is based on a temperature compensated

zener diode. The circuitry is fully active at supply voltages above +8 volts., and

provides up to 20mA of load current to external circuitry at +5.0 volts. In systems

where additional current is required, an external PNP transistor can be used to

boost the available current. A rugged low frequency audio-type transistor should

be used, and lead lengths between the PWM and transistor should be as short as

possible to minimize the risk of oscillations. Even so, some types of transistors

may require collector-base capacitance for stability. Up to 1amp of load current

can be obtained with excellent regulation if the device selected maintains high

current gain.

UNDERVOLTAGE LOCKOUT

The undervoltage lockout circuit protects the SG1526 and the power devices it controls from inadequate supply voltage. If

+V

while the control circuitry is stabilizing, and holds the soft-start timing capacitor in a discharged state.

The circuit consists of a +1.2 volt bandgap reference and comparator circuit which

is active when the reference voltage has risen to 3V

the reference voltage rises to approximately +4.4 volts, the circuit enables the

output drivers and releases the RESET pin, allowing a normal soft-start. The

comparator has 200mV of hysteresis to minimize oscillation at the trip point. When

+V

age circuit pulls RESET LOW again. The soft-start capacitor is immediately

discharged, and the PWM is ready for another soft-start cycle.

The SG1526 can operate from a +5 volt supply by connecting the V

+V

FIGURE 18.

SIMPLIFIED UNDERVOLTAGE LOCKOUT

SOFT-START CIRCUIT

The soft-start circuit protects the power transistors and rectifier diodes from high

current surges during power supply turn-on. When supply voltage is first applied

to the SG1526, the undervoltage lockout circuit holds RESET LOW with Q3. Q1

is turned on, which holds the soft-start capacitor voltage at zero. The second

collector of Q1 clamps the output error amplifier to ground, guaranteeing zero duty

cycle at the driver outputs. When the supply voltage reaches normal operating

range, RESET will go HIGH. Q1 turns off, allowing the internal 100µA current

source to charge C

Q2 clamps the error amplifier output to 1V

voltage on C

PWM linearly increases to whatever value the voltage regulation loop requires for

an error null. Figure 10 gives the timing relationship between C

to 100% duty cycle.

FIGURE 19.

SOFT-START CIRCUIT SCHEMATIC

FIGURE 20.

DIGITAL CONTROL PORT SCHEMATIC

DIGITAL CONTROL PORTS

The three digital control ports of the SG1526 are bi-directional. Each pin can drive

TTL and 5 volt CMOS logic directly, up to a fan-out of 10 low-power Schottky gates.

Each pin can also be directly driven by open-collector voltage comparators; fan-

in is equivalent to 1 low-power Schottky gate. Each port is normally HIGH; the pin

is pulled LOW to activate the particular function. Driving SYNC LOW initiates a

discharge cycle in the oscillator. Pulling SHUTDOWN LOW immediately inhibits

all PWM output pulses. Holding RESET LOW discharges the soft-start capacitor.

The logic threshold is +1.1 volts at 25°C. Noise immunity can be gained at the

expense of fan-out with an external 2K pullup resistor to +5 volts.

FIGURE 17.

EXTENDING REFERENCE OUTPUT CURRENT