WM8192

Product Preview

WOLFSON MICROELECTRONICS LTD

PP Rev 1.0 June 2000

20

DEVICE CONFIGURATION

REGISTER MAP

The following table describes the location of each control bit used to determine the operation of the

WM8192. The register map is programmed by writing the required codes to the appropriate

addresses via the serial interface.

BIT

ADDRESS

<a5:a0>

DESCRIPTION

DEF

(hex)

RW

b7

b6

b5

b4

b3

b2

b1

b0

000001

Setup Reg 1

03

RW

MODE4

PGAFS[1]

PGAFS[0]

SELPD

MONO

CDS

EN

000010

Setup Reg 2

20

RW

DEL[1]

DEL[0]

RLCDACRNG

0

VRLCEXT

INVOP

MUXOP

0

000011

Setup Reg 3

1F

RW

CHAN[1]

CHAN[0]

CDSREF [1]

CDSREF [0]

RLCV[3]

RLCV[2]

RLCV[1]

RLCV[0]

000100

Software Reset

00

W

000101

Auto-cycle Reset

00

W

000110

Setup Reg 4

00

RW

FM[1]

FM[0]

INTM[1]

INTM[0]

RLCINT

FME

ACYCNRLC

LINEBYLINE

000111

Revision Number

41

R

001000

Setup Reg 5

00

RW

0

0

0

POSNNEG

VDEL[2]

VDEL[1]

VDEL[0]

VSMPDET

001001

Setup Reg 6

00

RW

0

0

0

0

SELDIS[3]

SELDIS[2]

SELDIS[1]

SELDIS[0]

001010

Reserved

00

RW

0

0

0

0

0

0

0

0

001011

Reserved

00

RW

0

0

0

0

0

0

0

0

001100

Reserved

00

RW

0

0

0

0

0

0

0

0

100000

DAC Value (Red)

80

RW

DAC[7]

DAC[6]

DAC[5]

DAC[4]

DAC[3]

DAC[2]

DAC[1]

DAC[0]

100001

DAC Value

(Green)

80

RW

DAC[7]

DAC[6]

DAC[5]

DAC[4]

DAC[3]

DAC[2]

DAC[1]

DAC[0]

100010

DAC Value (Blue)

80

RW

DAC[7]

DAC[6]

DAC[5]

DAC[4]

DAC[3]

DAC[2]

DAC[1]

DAC[0]

100011

DAC Value (RGB)

80

W

DAC[7]

DAC[6]

DAC[5]

DAC[4]

DAC[3]

DAC[2]

DAC[1]

DAC[0]

101000

PGA Gain (Red)

00

RW

PGA[7]

PGA[6]

PGA[5]

PGA[4]

PGA[3]

PGA[2]

PGA[1]

PGA[0]

101001

PGA Gain

(Green)

00

RW

PGA[7]

PGA[6]

PGA[5]

PGA[4]

PGA[3]

PGA[2]

PGA[1]

PGA[0]

101010

PGA Gain (Blue)

00

RW

PGA[7]

PGA[6]

PGA[5]

PGA[4]

PGA[3]

PGA[2]

PGA[1]

PGA[0]

101011

PGA Gain (RGB)

00

W

PGA[7]

PGA[6]

PGA[5]

PGA[4]

PGA[3]

PGA[2]

PGA[1]

PGA[0]

Table 5 Register Map

REGISTER MAP DESCRIPTION

The following table describes the function of each of the control bits shown in Table 5.

REGISTER

BIT

NO

BIT

NAME(S)

DEFAULT

DESCRIPTION

0EN

1

Global power down: 0 = complete power down, 1 = fully active.

1

CDS

1

Select correlated double sampling mode: 0 = single ended mode,

1 = CDS mode.

2MONO

0

Mono/colour select: 0 = colour, 1 = monochrome operation.

3

SELPD

0

Selective power down: 0 = no individual control,

1 = individual blocks can be disabled (controlled by SELDIS[3:0]).

Offsets PGA output to optimise the ADC range for different polarity sensor

output signals. Zero differential PGA input signal gives:

5:4

PGAFS[1:0]

00

00 = Zero output

(use for bipolar video)

01 = Zero output

10 = Full-scale positive output

(use for negative going video)

11 = Full-scale negative output

(use for positive going video)

Setup

Register 1

6MODE4

0

Required when operating in MODE4: 0 = other modes, 1 = MODE4.