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BR24A Datasheet(PDF) 10 Page - Rohm

Part No. BR24A
Description  High Reliability Series EEPROMs I2C BUS
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Maker  ROHM [Rohm]
Homepage  http://www.rohm.com
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BR24A Datasheet(HTML) 10 Page - Rohm

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BR24A□□-WM series
Technical Note
10/17
www.rohm.com
2009.08 - Rev.C
© 2009 ROHM Co., Ltd. All rights reserved.
Read Command
Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be
read in succession.
In random read cycle, data of designated word address can be read.
When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next address
data can be read in succession.
Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H' .
When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
W ORD
A D D R ESS (n)
SD A
LIN E
A
C
K
A
C
K
DATA(n)
A
C
K
SLAV E
A D D R ESS
10
0
1
A 0
A1
A2
WA
7
A0
D0
SLAV E
A D D R ESS
10
0
1A1
A2
S
T
A
R
T
D7
R
/
W
R
E
A
D
WA
0
N ote)
*1
It is necessary to input 'H' to
the last ACK.
Fig.42 Random read cycle (BR24A01A/02/04/08/16-WM)
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
1st WORD
ADDRESS(n)
SDA
LINE
A
C
K
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
1 0
0
1
A0
A1
A2
D7
D0
*
2nd WORD
ADDRESS(n)
A
C
K
S
T
A
R
T
SLAVE
ADDRESS
1 0
0
1
A2A1
R
/
W
R
E
A
D
A0
WA
0
Note)
*1
WA
12
WA
11
**
Fig.43 Random read cycle (BR24A32/64 -WM)
*1 As for WA12, BR24A32-WM become Don’t care.
*1 As for WA7, BR24A01A-WM become Don’t care.
S
T
A
R
T
S
T
O
P
SDA
LIN E
A
C
K
D ATA(n)
A
C
K
SLA VE
ADDR ESS
10
0
1
A0
A1
A2
D 0
D7
R
/
W
R
E
A
D
Note)
Fig.44 Current read cycle
It is necessary to input 'H' to
the last ACK.
R
E
A
D
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
DATA(n)
SDA
LINE
A
C
K
A
C
K
DATA(n+x)
A
C
K
SLAVE
ADDRESS
10
0
1
A0
A1
A2
D0
D7
D0
D7
Note)
Fig.45 Sequential read cycle (in the case of current read cycle)
*1 In BR24A16-WM, A2 becomes P2.
*2 In BR24A08-WM, BR24A16-WM, A1 becomes P1.
*3 In BR24A04-WM, A0 becomes PS, and in BR24A08-WM
and BR24A16-WM, A0 becomes P0.
1 0
0
1A 0
A1
A2
*1 *2 *3
Note)
Fig.46 Difference of slave address of each type


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