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BR24A Datasheet(PDF) 8 Page - Rohm

Part No. BR24A
Description  High Reliability Series EEPROMs I2C BUS
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Maker  ROHM [Rohm]
Homepage  http://www.rohm.com
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BR24A Datasheet(HTML) 8 Page - Rohm

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BR24A□□-WM series
Technical Note
8/17
www.rohm.com
2009.08 - Rev.C
© 2009 ROHM Co., Ltd. All rights reserved.
Write Command
Write cycle
Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is
specified per device of each capacity. Up to 32 arbitrary bytes can be written. (In the case of BR24A32 / A64-WM)
Data is written to the address designated by word address (n-th address)
By issuing stop bit after 8bit data input, write to memory cell inside starts.
When internal write is started, command is not accepted for tWR (5ms at maximum).
By page write cycle, the following can be written in bulk : Up to 8 bytes ( BR24A01A-WM, BR24A02-WM)
: Up to 16bytes (BR24A04-WM, BR24A08-WM,BR24A16-WM)
: Up to 32bytes (BR24A32-WM, BR24A64-WM
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment" of "Notes on page write cycle" in P8/16.)
As for page write cycle of BR24A01A-WM and BR24A02-WM, after the significant 5 bits (4 significant bits in
BR24A01A-WM) of word address are designated arbitrarily, and as for page write command of BR24A04-WM,
BR24A08-WM, and BR24A16-WM, after page select bit (PS) of slave address is designated arbitrarily, by continuing data
input of 2 bytes or more, the address of insignificant 4 bits (insignificant 3 bit in BR24A01A-WM, and BR24A02-WM) is
incremented internally, and data up to 16 bytes (up to 8 bytes in BR24A01A-WM and BR24A02-WM) can be written.
As for page write cycle of BR24A32-WM and BR24A64-WM, after the significant 7 bits (in the case of BR24A32-WM) of
word address, or the significant 8 bits (in the case of BR24A64-WM) of word address are designated arbitrarily, by continuing data
input of 2 byte or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.
W
R
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T
E
S
T
A
R
T
R
/
W
A
C
K
S
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P
WO R D
ADD R ESS(n)
DATA (n)
SDA
LIN E
A
C
K
A
C
K
D A TA(n+15)
A
C
K
SLAVE
ADDR ESS
1 0
0
1A 0
A1
A2
WA
7
D0
D7
D 0
WA
0
Note)
*1
*2
A1
A2
WA
7
D7
1
1
0
0
W
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A
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/
W
S
T
O
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WORD
ADDRESS
DATA
SLAVE
ADDRESS
A0
WA
0
D0
A
C
K
SDA
LINE
A
C
K
A
C
K
Note)
*1
Fig.35 Byte write cycle (BR24A01A/02/04/08/16-WM)
*1 As for WA7, BR24A01A-WM becomes Don’t care.
A1
A2
1
1
0
0
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A
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S
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1st WORD
ADDRESS
DATA
SLAVE
ADDRESS
A0
D0
A
C
K
SDA
LINE
A
C
K
A
C
K
Note)
WA
12
WA
11
*
WA
0
A
C
K
2nd WORD
ADDRESS
D7
*1
*
*
*1 As for WA12, BR24A32-WM becomes Don’t care.
Fig.36 Byte write cycle (BR24A32/64-WM)
*1 As for WA7, BR24A01A-WM becomes Don’t care.
*2 As for BR24A01A/02-WM becomes (n+7).
Fig.37 Page write cycle (BR24A01A/02/04/08/16-WM)
Fig.38 Page write cycle (BR24A32/64-WM)
*1 As for WA12, BR24A32-WM becomes Don’t care.
W
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W
A
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S
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1st W O R D
AD D R ESS(n)
SD A
LIN E
A
C
K
A
C
K
D A TA (n+31)
A
C
K
SLAVE
AD D R ESS
1 0
0
1A 0
A1
A2
D0
Note)
*1
DA TA (n)
D0
D7
A
C
K
2nd W O R D
A D D R ESS(n)
WA
0
WA
12
WA
11
*
*
*
Note)
1 0
0
1A 0
A1
A2
*1 *2 *3
Fig.39 Difference of slave address of each type
*1 In BR24A16-WM, A2 becomes P2.
*2 In BR24A08-WM, BR24A16-WM, A1 becomes P1.
*3 In BR24A04-WM, A0 becomes PS, and in BR24A08-WM and
BR24A16-WM, A0 becomes P0.


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