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BR24A Datasheet(PDF) 7 Page - Rohm

Part No. BR24A
Description  High Reliability Series EEPROMs I2C BUS
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Maker  ROHM [Rohm]
Homepage  http://www.rohm.com
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BR24A Datasheet(HTML) 7 Page - Rohm

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BR24A□□-WM series
Technical Note
7/17
www.rohm.com
2009.08 - Rev.C
© 2009 ROHM Co., Ltd. All rights reserved.
I
2C BUS communication
I
2C BUS data communication
I
2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and
acknowledge is always required after each byte. I
2C BUS carries out data transmission with plural devices connected by
2 communication lines of serial data (SDA) and serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during
data communication is called “transmitter”, and the device that receives data is called “receiver”.
Start condition (Start bit recognition)
Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL
is
'HIGH' is necessary.
This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition
is satisfied, any command is executed.
Stop condition (stop bit recongnition)
Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
Acknowledge (ACK) signal
This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data
output of readcommand) at the transmitter (sending) side releases the bus after output of 8bit data.
The device (this IC at slave address input of write command, read command, and μ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this
IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop cindition (stop bit), and ends read action. And this IC gets in status.
Device addressing
Output slave address after start condition from master.
The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'.
Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same
bus according to the number of device addresses.
The most insignificant bit (R/W --- READ / WRITE) of slave address is used for designating write or read action, and is as
shown below.
Setting R / W to 0 ------- write (setting 0 to word address setting of random read)
Setting R / W to 1 ------- read
Type
Slave address
Maximum number of
connected buses
BR24A01A-WM
1 0 1 0
A2
A1
A0
R/W
8
BR24A02-WM
1 0 1 0
A2
A1
A0
R/W
8
BR24A04-WM
1 0 1 0
A2
A1
PS
R/W
4
BR24A08-WM
1 0 1 0
A2
P1
P0
R/W
2
BR24A16-WM
1 0 1 0
P2
P1
P0
R/W
1
BR24A32-WM
1 0 1 0
A2
A1
A0
R/W
8
BR24A64-WM
1 0 1 0
A2
A1
A0
R/W
8
PS, P0~P2 are page select bits.
Note) Up to 4 units BR24A04-WM, up to 2 units of BR24A08-WM, and one unit of BR24A16-WM can be connected.
Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.
Fig.34 Data transfer timing
1
2
3
4
8
6
5
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
A0
7
A1
A2
GND
Vcc
WP
SCL
SDA
89
89
89
S
P
condition
condition
ACK
STOP
ACK
DATA
DATA
ADDRESS
START
R/W
ACK
1-7
SDA
SCL
1-7
1-7


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