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BD9018KV Datasheet(PDF) 5 Page - Rohm

Part # BD9018KV
Description  Step-down,High-efficiency Switching Regulators (Controller type)
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Manufacturer  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BD9018KV Datasheet(HTML) 5 Page - Rohm

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Technical Note
5/16
BD9018KV
www.rohm.com
2010.02 - Rev.A
c
2010 ROHM Co., Ltd. All rights reserved.
Block functional descriptions
Error amp
The error amp compares output feedback voltage to the 0.8V reference voltage and provides the comparison result as COMP voltage, which
is used to determine the switching Duty. COMP voltage is limited to the SS voltage, since soft start at power up is based on SS pin voltage.
Oscillator (OSC)
Oscillation frequency is determined by the switching frequency pin (RT) in this block. The frequency can be set between 250 kHz and 550
kHz.
The phase difference between each output is 180deg.
SLOPE
The SLOPE block uses the clock produced by the oscillator to generate a triangular wave, and sends the wave to the PWM comparator.
PWM COMP
The PWM comparator determines switching Duty by comparing the COMP voltage, output from the error amp, with the triangular wave from
the SLOPE block. Switching duty is limited to a percentage of the internal maximum duty, and thus cannot be 100% of the maximum.
Reference voltage (VREG5)
This block generates the internal reference voltage: 5V. The external capacitor is necessary for VREG5. Moreover, the external capacitor
should
be set to VREG5A which is FET drive REG input. It is recommended to use the ceramic capacitor that is low ESR and 6.6μF~12
μ
F according to VREG5 and VREG5A.
External synchronization (SYNC)
When pulses are supplied to the SYNC terminal, the internal frequency synchronizes with the frequency of the supplied pulses. When
synchronized with SYNC, 1ch is turned on with the rising edge of SYNC and 2ch is turned on with the falling edge of SYNC so that the phase
difference between each output depends on the Duty of SYNC.
The pulse width needs to be more than 200nsec for both on time and off time. Supply a pulse wave faster than the frequency
determined with the setting resistor (RT), but slower than 600 kHz (Fosc×1.5 or less). Moreover, it is recommended to insert the low pass
filter to
the SYNC terminal. (Refer to Fig.13)
Over current protection (OCP)
The over current protection is activated when the VCCCL-CL voltage reaches or exceeds 90mV. When the over current protection is active,
Duty is low, and the output voltage also decreases.
Short circuit protection (SCP)
After activating the over current protection and if the output voltage falls below 70%, then the short circuit protection will be activated. When
the short circuit protection is active, the output is turned off for 32 pulses of the oscillation frequency, and the SS and COMP are discharged.
Protection circuits (UVLO/TSD)
The UVLO lock out function is activated when VREG5 falls to about 3.7V. The TSD turns outputs OFF when the chip temperature reaches or
exceeds 150℃. Output is restored when the temperature drops below the threshold value.
Power GOOD (PGOOD)terminal
The UVLO lock out function is activated when VREG5 falls to about 3.7V. The TSD turns outputs OFF when the chip temperature reaches or
exceeds 150℃. Output is restored when the temperature drops below the threshold value.
Application circuit example
Fig. 13(Step-Down)
There are many factors (PCB board layout, Output Current, etc.) that can affect the DCDC characteristics.
Please verify and confirm using practical applications.
SW1
DGND1
OUTL1
VREG5A
FB1
COMP1
SS1
SW2
PGOOD
DGND2
OUTL2
VREG5
EXTVCC
FB2
COMP2
SS2
OUTH1
OUTH2
22nF
4.7uF
1kΩ
10000pF
22nuF
1uF
23mΩ
23mΩ
1uF
4.7uF
3.3kΩ 3300pF
13kΩ
68
30uF
(C2012JB
0J106K
TDK)
30uF
(C2012JB
0J106K
TDK)
15kΩ
Vo(3.3V/2A)
RB051
L-40
RB051
L-40
10uH
Vo(5V/2A)
SP8K2
SP8K2
VIN(12V)
5
48
0.1
uF
0.1
uF
12
11
8
7
3
2
1
47
44
41
39
38
37
36
33
30
13
15
17
21
22
14
46
23
100Ω
1nF
1nF
100Ω
330pF
47kΩ
150Ω
3300pF
330pF
1000pF
510Ω
10uH
RB160
VA-40
RB160
VA-40
10
100uF
100kΩ
34
27
26
(SLF10145:TDK)
(SLF10145:TDK)
2kΩ
33pF


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