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## ADP1871 Datasheet(HTML) 21 Page - Analog Devices

 21 / 44 pageADP1870/ADP1871Rev. 0 | Page 21 of 44When the desired valley current limit (ICLIM) has been determined,the current-sense gain can be calculated as follows:The valley current limit is programmed as outlined in Table 7and Figure 71. The inductor chosen must be rated to handle thepeak current, which is equal to the valley current from Table 7plus the peak-to-peak inductor ripple current (see the InductorSelection section). In addition, the peak current value must beused to compute the worst-case power dissipation in theMOSFETs (see Figure 72).ONCSCLIMRAI×=V4.1where:RON is the channel impedance of the lower-side MOSFET.ACS is the current-sense gain multiplier (see Table 6 and Table 7).INDUCTORCURRENTVALLEY CURRENT-LIMITTHRESHOLD (SET FOR 25A)ΔI = 33%OF 30ACOMPOUTPUTSWINGCOMPOUTPUT2.4V1V0A35A30A32.25A37A49A39.5AΔI = 45%OF 32.25AΔI = 65%OF 37AMAXIMUM DC LOADCURRENTAlthough the ADP1870/ADP1871 have only four discrete current-sense gain settings for a given RON variable, Table 7 and Figure 71outline several available options for the valley current setpointbased on various RON values.Table 7. Valley Current Limit Program1RON(mΩ)Valley Current Level47 kΩ22 kΩOpen100 kΩACS = 3 V/VACS = 6 V/VACS = 12 V/VACS = 24 V/V1.538.9229.22.523.3339.019.53.533.416.74.526.013523.411.75.521.2510.61023.311.75.831531.015.57.757.51826.013.06.53.25Figure 72. Valley Current-Limit Threshold in Relation to Inductor Ripple CurrentHICCUP MODE DURING SHORT CIRCUITA current-limit violation occurs when the current across thesource and drain of the lower-side MOSFET exceeds thecurrent-limit setpoint. When 32 current-limit violations aredetected, the controller enters idle mode and turns off theMOSFETs for 6 ms, allowing the converter to cool down. Then,the controller reestablishes soft start and begins to cause theoutput to ramp up again (see Figure 73). While the outputramps up, COMP is monitored to determine if the violation isstill present. If it is still present, the idle event occurs again,followed by the full-chip power-down sequence. This cyclecontinues until the violation no longer exists. If the violationdisappears, the converter is allowed to switch normally,maintaining regulation.1 Refer to Figure 71 for more information and a graphical representation.123456789 10 11 12 13 14 15 16 17 18 19 20RON (mΩ)3937353331292725232119171513119753RES = 47kΩACS = 3V/VRES = 22kΩACS = 6V/VRES = NO RESACS = 12V/VRES = 100kΩACS = 24V/VFigure 71. Valley Current-Limit Value vs. RON of the Lower-Side MOSFETfor Each Programming Resistor (RES)HSCLIMZEROCURRENTREPEATED CURRENT-LIMITVIOLATION DETECTEDA PREDETERMINED NUMBEROF PULSES IS COUNTED TOALLOW THE CONVERTERTO COOL DOWNSOFT START ISREINITIALIZED TOMONITOR IF THEVIOLATIONSTILL EXISTSFigure 73. Idle Mode Entry Sequence Due to Current-Limit Violation

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