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UCC28950PWTR Datasheet(PDF) 13 Page - Texas Instruments |
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UCC28950PWTR Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 42 page  OUTA (OUTC) OUTB (OUTD) T ABSET1 T CDSET1 T ABSET2 T CDSET2 T ABSET2 T CDSET2 T ABSET1 T CDSET1 UCC28950 www.ti.com SLUSA16 – MARCH 2010 Adaptive Delay, (Delay between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL)) The resistor RAB from the DELAB pin, DELAB to GND, along with the resistor divider RAHI from CS pin to ADEL pin and RA from ADEL pin to GND sets the delay TABSET between one of outputs OUTA or OUTB going low and another output going high Figure 3. Figure 3. Delay definitions between OUTA and OUTB, OUTC and OUTD This delay gradually increases as a function of the CS signal from TABSET1, which is measured at VCS = 1.8 V, to TABSET2, which is measured at the VCS = 0.2 V. This approach ensures there will be no shoot-through current during the high-side and low-side MOSFET switching and optimizes the delay for ZVS condition over a wide load current range. Depending on the resistor divider RAHI and RA, the proportional ratio between longest and shortest delay is set. The max ratio is achieved by tying the CS and ADEL pins together. If ADEL is connected to GND, then the delay is fixed, defined only by the resistor RAB from DELAB to GND. The delay TCDSET1 and TCDSET2 settings and their behaviour for outputs OUTC and OUTD are very similar to the one described for OUTA and OUTB. The difference is that resistor RCD connected between DELCD pin and GND sets the delay TCDSET. Delays for outputs OUTC and OUTD share with the outputs OUTA and OUTB the same CS voltage dependence pin ADEL. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link(s): UCC28950 |
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