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P2V28S20ATP-7 Datasheet(PDF) 7 Page - Vanguard International Semiconductor |
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P2V28S20ATP-7 Datasheet(HTML) 7 Page - Vanguard International Semiconductor |
7 / 51 page 128Mb Synchronous DRAM JULY.2000 Rev.2.2 P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT) Page-6 H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-A9 =0, A0-A6 =Mode Address COMMAND TRUTH TABLE COMMAND MNEMONIC CKE n-1 CKE n /CS /RAS /CAS /WE BA0,1 A1 1 A1 0 A0-9 DESEL H X H X X X X XXX No Operation NOP HX L H H H X X X X ACT H X L L H H V VVV PRE H X LLH L V X L X PREA H X LLH L X H X WRIT E H X L H L L VVL V WRITE A HX LH L L V V H V READ H X L H L H VVL V READA HX LH L H V V H V Auto-Refresh REFA H H L L L H X XXX Self-Refresh Entry REFS H L L L L H X XXX Self-Refresh Exit REFSX L H H X X X X XXX L H L H H H X XXX Mode Register Set MRS H X L L L L L L L V*1 X Burst Terminate TBST HX L HHL X X X X Deselect Row Address Entry & Bank Active Single Bank Precharge Precharge All Banks Column Address Entry &Write Column Address Entry & Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with Auto-Precharge |
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