HYMD264726B(L)8J-J

Rev. 0.1/Oct. 02

10

- continued -

Note :

1.

This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

2.

Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.

3.

For command/address input slew rate >=1.0V/ns

4.

For command/address input slew rate >=0.5V/ns and <1.0V/ns

This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.

Input Setup / Hold Slew-rate Derating Table.

5.

CK, /CK slew rates are >=1.0V/ns

6.

These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by

design or tester correlation.

7.

Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.

8.

Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete

Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

Parameter

Symbol

DDR333

Unit

Note

Min

Max

Input Pulse Width

2.2

ns

6

Write DQS High Level Width

0.35

-

CK

Write DQS Low Level Width

0.35

-

CK

Clock to First Rising edge of DQS-In

0.75

1.25

CK

Data-In Setup Time to DQS-In (DQ & DM)

0.45

-

ns

6,7, 11~13

Data-in Hold Time to DQS-In (DQ & DM)

0.45

-

ns

6,7, 11~13

DQ & DM Input Pulse Width

1.75

-

ns

Read DQS Preamble Time

0.9

1.1

CK

Read DQS Postamble Time

0.4

0.6

CK

Write DQS Preamble Setup Time

0-

CK

Write DQS Preamble Hold Time

0.25

-

CK

Write DQS Postamble Time

0.4

0.6

CK

Mode Register Set Delay

2-

CK

Exit Self Refresh to Any Execute Command

200

-

CK

8

Average Periodic Refresh Interval

-7.8

us

Input Setup / Hold Slew-rate

Delta tIS

Delta tIH

V/ns

ps

ps

0.5

0

0

0.4

+50

0

0.3

+100

0