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HY5PS12421F-E3 Datasheet(PDF) 32 Page - Hynix Semiconductor

Part # HY5PS12421F-E3
Description  512Mb DDR2 SDRAM
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HY5PS12421F-E3 Datasheet(HTML) 32 Page - Hynix Semiconductor

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Rev. 1.4 / July 2006
32
1HY5PS12421(L)F
HY5PS12821(L)F
HY5PS121621(L)F
10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
11. MIN ( t CL, t CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the
device (i.e. this value can be greater than the minimum specification limits for t CL and t CH). For example, t CL and t
CH are = 50% of the period, less the half period jitter ( t JIT(HP)) of the clock source, and less the half period jitter due
to crosstalk ( t JIT(crosstalk)) into the clock traces.
12. t QH = t HP – t QHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transi-
tion, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel varia-
tion of the output drivers.
13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output
drivers as well as output slew rate mismatch between DQS/ DQS and associated DQ in any given cycle.
14. t DAL = (nWR) + ( tRP/tCK):
For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application
clock period. nWR refers to the t WR parameter stored in the MRS.
Example: For DDR533 at t CK = 3.75 ns with t WR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks =4
+(4)clocks=8clocks.
15. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of
clock frequency change during precharge power-down, a specific procedure is required as described in section 2.9.
16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
17. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
18. tHZ and tLZ transitions occur in the same access time as valid data transitions. Thesed parameters are
referenced to a specific voltage level which specifies when the device output is no longer driving(tHZ), or begins driving
(tLZ). Below figure shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ)
by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device
output is no longer driving (tRPST), or begins driving (tRPRE). Below figure shows a method to calculate these points
when the device is no longer driving (tRPST), or begins driving (tRPRE). Below Figure shows a method to calculate
different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent.


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