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HY5PS12421F-E3 Datasheet(PDF) 12 Page - Hynix Semiconductor

Part # HY5PS12421F-E3
Description  512Mb DDR2 SDRAM
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HY5PS12421F-E3 Datasheet(HTML) 12 Page - Hynix Semiconductor

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Rev. 1.4 / July 2006
12
1HY5PS12421(L)F
HY5PS12821(L)F
HY5PS121621(L)F
3.2.1 Input DC Logic Level
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
Notes:
1.
Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
2.
The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range
from VREF to VIL(ac) max for falling edges as shown in the below figure.
3.
AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to
VIL(ac) on the negative transitions.
Symbol
Parameter
Min.
Max.
Units
Notes
VIH(dc)
dc input logic high
VREF + 0.125
VDDQ + 0.3
V
VIL(dc)
dc input logic low
- 0.3
VREF - 0.125
V
Symbol
Parameter
Min.
Max.
Units
Notes
V
IH (ac)
ac input logic high
VREF + 0.250
-
V
V
IL (ac)
ac input logic low
-VREF - 0.250
V
Symbol
Condition
Value
Units
Notes
VREF
Input reference voltage
0.5 * VDDQ
V1
VSWING(MAX)
Input signal maximum peak to peak swing
1.0
V
1
SLEW
Input signal minimum slew rate
1.0
V/ns
2, 3
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
VSWING(MAX)
delta TR
delta TF
VREF - VIL(ac) max
delta TF
Falling Slew =
Rising Slew =
VIH(ac)min - VREF
delta TR
3.2 DC & AC Logic Input Levels
< Figure : AC Input Test Signal Waveform>


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