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HY5DU561622FTP-5I Datasheet(PDF) 24 Page - Hynix Semiconductor

Part No. HY5DU561622FTP-5I
Description  256M(16Mx16) DDR SDRAM
Download  28 Pages
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Maker  HYNIX [Hynix Semiconductor]
Homepage  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HY5DU561622FTP-5I Datasheet(HTML) 24 Page - Hynix Semiconductor

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Rev. 1.1 / Mar. 2008
24
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter
Symbol
4
5
Unit
Note
Min
Max
Min
Max
Row Cycle Time
(Manual Precharge)
tRC
15
-
12
-
CK
Row Cycle Time
(Auto Precharge)
tRC_APCG
17
-
14
-
CK
Auto Refresh Row Cycle Time
tRFC
18
-
14
-
CK
Row Active Time
tRAS
40
70K
40
70K
ns
Row Address to Column Address Delay
tRCDRD
5-
4-
CK
tRCDWT
2-
2-
CK
Row Active to Row Active Delay
tRRD
2-
2-
CK
Column Address to Column Address Delay
tCCD
1-
1-
CK
Row Precharge Time
tRP
5-
4-
CK
Last Data-In to Precharge Delay
(Write Recovery Time : tWR)
tDPL
4-
3-
CK
Last Data-In to Read Command
tDRL
2-
2-
CK
Auto Precharge Write Recovery +
Precharge
Time
tDAL
9-
7-
CK
System Clock Cycle Time
CL = 4.0
tCK
4.0
7.0
-
-
ns
CL = 3.0
-
-
5.0
7.0
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
CK
Data-Out edge to Clock edge Skew
tAC
-0.7
0.7
-0.7
0.7
ns
DQS-Out edge to Clock edge Skew
tDQSCK
-0.7
0.7
-0.7
0.7
ns
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.4
-
0.45
ns
Data-Out hold time from DQS
tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-ns
1, 6
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-ns
1, 5
Data Hold Skew Factor
tQHS
-0.4
-0.5
ns
6
Input Setup Time
tIS
0.75
-
0.75
-
ns
2
Input Hold Time
tIH
0.75
-
0.75
-
ns
2
Write DQS High Level Width
tDQSH
0.4
0.6
0.4
0.6
CK
Write DQS Low Level Width
tDQSL
0.4
0.6
0.4
0.6
CK
Clock to First Rising edge of DQS-In
tDQSS
0.85
1.15
0.75
1.25
CK
Data-In Setup Time to DQS-In (DQ & DM)
tDS
0.4
-
0.4
-
ns
3


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