Rev. 1.1 / Mar. 2008

19

HY5DU561622FTP-4I

availability of the first burst of output data. The latency can be programmed 3 or 4 or 5 clocks.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident

with clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

DLL RESET

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon return-

ing to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically

disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any

time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally

applied clock before an any command can be issued.

OUTPUT DRIVER IMPEDANCE CONTROL

The HY5DU561622FTP supports Full, Half strength driver and Matched impedance driver, intended for lighter load and/

or point-to-point environments. The Full drive strength for all output is specified to be SSTL_2, CLASS II. Half strength

driver is to define about 50% of Full drive strength and Matched impedance driver, about 30% of Full drive strength.