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H55S2562JFR-60M Datasheet(PDF) 25 Page - Hynix Semiconductor

Part # H55S2562JFR-60M
Description  256MBit MOBILE SDR SDRAM based on 4M x 4Bank x16 I/O
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H55S2562JFR-60M Datasheet(HTML) 25 Page - Hynix Semiconductor

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Rev 1.1 / July. 2009
25
11
256Mbit (16Mx16bit) Mobile SDR
H55S2562JFR Series
CKE Enable(CKE) Truth TABLE (Sheet 2 of 2)
Note:
1. For the given current state CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode,
a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high.
3. The address inputs depend on the command that is issued.
4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered
from the all banks idle state.
5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of
clock after CKE goes high and is maintained for a minimum 200usec.
Current
State
CKE
Command
Action
Notes
Previous
Cycle
Current
Cycle
CS
RAS
CAS
WE
BA0,
BA1
A
max-
A0
All
Banks
Idle
H
H
H
X
X
X
Refer to the idle State section
of the Current State
Truth Table
3
H
H
L
H
X
X
3
H
H
L
L
H
X
3
H
H
L
L
L
H
X
X
Auto Refresh
H
H
L
L
L
L
OP CODE
Mode Register Set
4
H
L
H
X
X
X
Refer to the idle State section
of the Current State
Truth Table
3
H
L
L
H
X
X
3
H
L
L
L
H
X
3
H
L
L
L
L
H
X
X
Entry Self Refresh
4
H
L
L
L
L
L
OP CODE
Mode Register Set
L
X
X
X
X
X
X
X
Power Down
4
Any State
other than
listed above
H
H
X
X
X
X
X
X
Refer to operations of
the Current State
Truth Table
H
L
X
X
X
X
X
X
Begin Clock Suspend
next cycle
L
H
X
X
X
X
X
X
Exit Clock Suspend
next cycle
L
L
X
X
X
X
X
X
Maintain Clock Suspend


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