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H5RS5223CFR-11C Datasheet(PDF) 9 Page - Hynix Semiconductor |
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H5RS5223CFR-11C Datasheet(HTML) 9 Page - Hynix Semiconductor |
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9 / 66 page  Rev.1.5 / Jul. 2008 9 H5RS5223CFR ODT Updating The GDDR3 SDRAM uses programmable impedance output buffers. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor (RQ) is connected between the ZQ pin and VSSQ. The value of the resistor must be six times the desired driver impedance. For example, a 240 Ω. resistor is required for an output impedance of 40Ω. To ensure that output impedance is one-sixth the value of RQ (within 10 percent), RQ should be in the range of 210 Ω. to 270Ω. (30Ω. - 50Ω. output impedance). CK and CK# are not internally terminated. CK and CK# will be terminated on the system module using external 1% resistors. The output impedance and on die termination is updated during every AUTO REFRRESH commands to compensate for variations in supply voltage and temperature. The output impedance updates are transparent to the system. Impedance updates do not affect device operation, and all datasheet timings and current specifications are met during an update. A maximum of eight AUTO REFRESH commands can be posted to any given GDDR3 SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 x 3.9us (31.2us). This maximum abso- lute interval guarantees that the output drivers and the on die terminations of GDDR3 SDRAMs are recalibrated often enough to keep the impedance characteristics of those within the specified boundaries. ODT Control Bus snooping for READ commands other than CS# is used to control the on die termination in the dual load configuration. The GDDR3 SGRAM will disable the DQ and RDQS on die termination when a READ command is detected regardless of the state of CS#. The on die termination is disabled x clocks after the READ command where x equals CL-1 and stay off for a duration of BL/2+2CK. In a two-rank system, both DRAM devices snoop the bus for READ commands to either device and both will disable the on die termina- tion, for the DQ and DQS pins if a READ command is detected. The on die termination for all other pins on the device is always turned-on for both a single-rank system and a dual-rank system unless it is turned off in the EMRS. Only DQ,WDQS and DM pins can turn off through the EMRS. |
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