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H5PS5162FFR-S5 Datasheet(PDF) 6 Page - Hynix Semiconductor |
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H5PS5162FFR-S5 Datasheet(HTML) 6 Page - Hynix Semiconductor |
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6 / 39 page  Rev. 1.0 / July. 2008 6 Release H5PS5162FFR series 1.3 PIN DESCRIPTION PIN TYPE DESCRIPTION CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). CKE Input Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CS Input Chip Select : All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. ODT Input On Die Termination Control : ODT(registered HIGH) enables on die termination resis- tance internal to the DDR2 SDRAM. For x16 configuration ODT is applied to each DQ, UDQS/UDQS.LDQS/LDQS, UDM and LDM signal. The ODT pin will be ignored if the Extended Mode Register(EMRS(1)) is programmed to disable ODT. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM (LDM, UDM) Input Input Data Mask : DM is an input mask signal for write data. Input Data is masked when DM is sampled High coincident with that input data during a WRITE access. DM is sampled on both edges of DQS, Although DM pins are input only, the DM loading matches the DQ and DQS loading. BA0 - BA1 Input Bank Address Inputs: BA0 - BA1 define to which bank an ACTIVE, Read, Write or PRE- CHARGE command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. A0 -A12 Input Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0- BA1. The address inputs also provide the op code during MODE REGISTER SET com- mands. DQ Input/ Output Data input / output : Bi-directional data bus |
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