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H5RS5223CFR-N3C Datasheet(PDF) 3 Page - Hynix Semiconductor |
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H5RS5223CFR-N3C Datasheet(HTML) 3 Page - Hynix Semiconductor |
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3 / 66 page  Rev.1.5 / Jul. 2008 3 H5RS5223CFR DESCRIPTION The Hynix H5RS5223 is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The Hynix H5RS5223 is internally configured as a eight-bank DRAM. The Hynix H5RS5223 uses a double data rate architecture to achieve high-speed opreration. The double date rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the Hynix H5RS5223 consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the Hynix H5RS5223 is burst oriented; accesses start at a selected locations and continue for a programmed number of locations in a pro- grammed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ of WRITE com- mand. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0,BA1, BA2 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the Hynix H5RS5223 must be initial- ized. FEATURES Note) Above Hynix P/N’s and their homogeneous Subcomponents are RoHS (& Lead free) compliant ORDERING INFORMATION Part No. Power Supply Clock Frequency Max Data Rate Interface Package H5RS5223CFR-N3C VDD/VDDQ=2.05V 1300MHz 2600Mbps/pin POD_18 10mmx14mm 136Ball FBGA H5RS5223CFR-N2C 1200MHz 2400Mbps/pin H5RS5223CFR-N0C 1000MHz 2000Mbps/pin H5RS5223CFR-11C VDD/VDDQ=1.8V 900MHz 1800Mbps/pin H5RS5223CFR-14C 700MHz 1400Mbps/pin H5RS5223CFR-20C 500MHz 1000Mbps/pin H5RS5223CFR-14L VDD/VDDQ=1.5V 700MHz 1400Mbps/pin POD_15 H5RS5223CFR-18C 550MHz 1100Mbps/pin • 2.05V/ 1.8V/ 1.5V power supply supports (For more detail, Please see the Table 12 on page 43) • Single ended READ Strobe (RDQS) per byte • Single ended WRITE Strobe (WDQS) per byte • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle •On Die Termination • Output Driver Strength adjustment by EMRS • Calibrated output driver • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge • RDQS edge-aligned with data for READ; with WDQS center-aligned with data for WRITE • 8 internal banks for concurrent operation • CAS Latency: 4~11 (clock) • Data mask (DM) for masking WRITE data • 4n prefetch • Programmable burst lengths: 4, 8 • 32ms, 8K-cycle auto refresh • Auto precharge option • Auto Refresh and Self Refresh Modes • 1.8V Pseudo Open Drain I/O • Concurrent Auto Precharge support • tRAS lockout support, Active Termination support • Programmable Write latency(1, 2, 3, 4, 5, 6) • Boundary Scan Function with SEN pin • Mirror Function with MF pin |
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