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H5MS1262EFP-K3M Datasheet(PDF) 20 Page - Hynix Semiconductor |
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H5MS1262EFP-K3M Datasheet(HTML) 20 Page - Hynix Semiconductor |
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20 / 62 page  Rev 1.1 / July. 2009 20 Mobile DDR SDRAM 128Mbit (8M x 16bit) H5MS1262EFP Series Leakage Current Note: 1. All voltages are referenced to VSS = 0V and VSSQ must be same potential and VDDQ must not exceed the level of VDD. 2. VID(DC) and VID(AC) are the magnitude of the difference between the input level on CK and the input level on CK. 3. The value of VIX is expected to be 0.5*VDDQ and must track variations in the DC level of the same. 4. VIN = 0 to 1.8V. All other pins are not tested under VIN=0V. 5. DOUT is disabled. VOUT= 0 to 1.95V. AC OPERATING TEST CONDITION Note: 1. The circuit shown on the right represents the timing load used in defining the relevant timing parameters of the part. It is not intended to be either a precise repre- sentation of the typical system environment nor a depic- tion of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to system environ- ment. Manufacturers will correlate to their production (generally a coaxial transmission line terminated at the tester electronics). For the half strength driver with a nominal 10pF load parameters tAC and tQH are expected to be in the same range. However, these parameters are not subject to production test but are estimated by design and characterization. Use of IBIS or other simulation tools for system design validation is suggested. Input / Output Capacitance Note: 1. These values are guaranteed by design and are tested on a sample base only. 2. These capacitance values are for single monolithic devices only. Multiple die packages will have parallel capacitive loads. 3. Input capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. VDD, VDDQ are applied and all other pins (except the pin under test) floating. DQ 's should be in high impedance state. This may be achieved by pulling CKE to low level. 4. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match signal propagation times of DQ, DQS and DM in the system. Parameter Symbol Min Max Unit Note Input Leakage Current ILI -1 1 uA 4 Output Leakage Current ILO -1.5 1.5 uA 5 Parameter Symbol Value Unit Note AC Input High/Low Level Voltage VIH / VIL 0.8*VDDQ/0.2*VDDQ V Input Timing Measurement Reference Level Voltage Vtrip 0.5*VDDQ V Input Rise/Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voltage Voutref 0.5*VDDQ V Output Load Capacitance for Access Time Measurement CL pF 1 Parameter Symbol Speed Unit Note Min Max Input capacitance, CK, CK CCK 1.5 3.5 pF Input capacitance delta, CK, CK CDCK - 0.25 pF Input capacitance, all other input-only pins CI 1.5 3.0 pF Input capacitance delta, all other input-only pins CDI - 0.5 pF Input/output capacitance, DQ, DM, DQS CIO 2.0 4.5 pF 4 Input/output capacitance delta, DQ, DM, DQS CDIO - 0.5 pF 4 Test Load for Full Drive Strength Buffer (20 pF) Test Load for Half Drive Strength Buffer (10 pF) Output Output Output Output ZO=50 |
Similar Part No. - H5MS1262EFP-K3M |
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Similar Description - H5MS1262EFP-K3M |
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