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H5MS2562JFR-E3M Datasheet(PDF) 5 Page - Hynix Semiconductor |
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H5MS2562JFR-E3M Datasheet(HTML) 5 Page - Hynix Semiconductor |
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5 / 62 page  Rev 1.2 / July. 2009 5 Mobile DDR SDRAM 256Mbit (16M x 16bit) H5MS2562JFR Series The Hynix H5MS2562JFR series has the special Low Power function of Auto TCSR (Temperature Compensated Self Refresh) to reduce self refresh current consumption. Since an internal temperature sensor is implemented, it enables to automatically adjust refresh rate according to temperature without external EMRS command. Deep Power Down Mode is an additional operating mode for Low Power DDR SDRAM (Mobile DDR SDRAM). This mode can achieve maximum power reduction by removing power to the memory array within Low Power DDR SDRAM (Mobile DDR SDRAM). By using this feature, the system can cut off almost all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout flexibility. All inputs are LVCMOS compatible. Devices will have a VDD and VDDQ supply of 1.8V (nominal). The Hynix H5MS2562JFR series is available in the following package: - 60Ball FBGA [8mm x 10mm, t=1.0mm max] 256Mb Mobile DDR SDRAM ORDERING INFORMATION Part Number Clock Frequency Organiza- tion Interface Operating temperature Package H5MS2562JFR-E3M 200MHz(CL3) / 83MHz(CL2) 4banks x 4Mb x 16 LVCMOS Mobile Temp (-30 oC ~ 85oC) Lead & Halogen Free H5MS2562JFR-J3M 166MHz(CL3) / 83MHz(CL2) H5MS2562JFR-K3M 133MHz(CL3) / 83MHz(CL2) H5MS2562JFR-L3M 100MHz(CL3) / 66MHz(CL2) |
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