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H5MS1262EFP-K3E Datasheet(PDF) 59 Page - Hynix Semiconductor

Part # H5MS1262EFP-K3E
Description  128M (8Mx16bit) Mobile DDR SDRAM
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5MS1262EFP-K3E Datasheet(HTML) 59 Page - Hynix Semiconductor

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Rev 1.1 / July. 2009
59
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Data mask1,2)
Mobile DDR SDRAM uses a DQ write mask enable signal (DM) which masks write data.
Data masking is only available in the write cycle for Mobile DDR SDRAM. Data masking is available during write, but
data masking during read is not available.
DM command masks burst write data with reference to data strobe signal and it is not related with read data. DM com-
mand can be initiated at both the rising edge and the falling edge of the DQS. DM latency for write operation is zero.
For x16 data I/O, Mobile DDR SDRAM is equipped with LDM and UDM which control DQ0~DQ7 and DQ8~DQ15
respectively.
Note:
1) Mobile SDR SDRAM can mask both read and write data, but the read mask is not supported by Mobile DDR SDRAM.
2) Differences in Functions and Specifications (next table)
Data Masking (Write cycle: BL=4)
Item
Mobile DDR SDRAM
Mobile SDR SDRAM
Data mask
Write mask only
Write mask/Read mask
WRITE
WRITE
DM
CMD
CK
CK
D0
D1
D3
D0
D1
D3
Hi-
Z
DQS
DQ
Data
Masking
Data
Masking
tDQSS
tDQSL
tDS
tDH
tDQSH
Hi-
Z


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