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H5MS1262EFP-K3E Datasheet(PDF) 52 Page - Hynix Semiconductor |
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H5MS1262EFP-K3E Datasheet(HTML) 52 Page - Hynix Semiconductor |
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52 / 62 page  Rev 1.1 / July. 2009 52 Mobile DDR SDRAM 128Mbit (8M x 16bit) H5MS1262EFP Series Mode Register The mode register contains the specific mode of operation of the Mobile DDR SDRAM. This register includes the selec- tion of a burst length(2, 4 or 8), a cas latency(2 or 3), a burst type. The mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execution of mode register set command. Mode Register Set BURST LENGTH Read and write accesses to the Mobile DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Page10. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. BURST TYPE Accesses within a given burst may be programmed to be either sequential or interleaved. CAS LATENCY The CAS latency is the delay between the registration of a READ command and the availability of the first piece of out- put data. If a READ command is registered at a clock edge n and the latency is 3 clocks, the first data element will be valid at n + 2tCK + tAC. If a READ command is registered at a clock edge n and the latency is 2 clocks, the first data element will be valid at n + tCK + tAC. CLK CLK Precharge All Bank Mode Register Set CM D tCK Comm and (any) 0 1 2 3 4 5 6 tRP 2 CLK m in |
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