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H5MS1222EFP-Q3E Datasheet(PDF) 29 Page - Hynix Semiconductor |
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H5MS1222EFP-Q3E Datasheet(HTML) 29 Page - Hynix Semiconductor |
29 / 62 page Rev 1.0 / Jun. 2008 29 Mobile DDR SDRAM 128Mbit (4M x 32bit) H5MS1222EFP Series Once a row is Open (with an ACTIVE command) a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD ( MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been closed (precharge). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to differ- ent banks is defined by tRRD. Don't Care Once a row is Open(with an ACTIVE command) a READ or W RITE command may be issued to that row , subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or W RITE command can be entered . /CLK CLK NOP NOP NOP NOP tRCD Command Address Write A With A/P Bank B ACT NOP Bank A ACT Bank A Col Bank B Row Bank A Row Bank A ACT Bank A Row tRRD tRC |
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