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H5MS1G22MFP-L3M Datasheet(PDF) 61 Page - Hynix Semiconductor |
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H5MS1G22MFP-L3M Datasheet(HTML) 61 Page - Hynix Semiconductor |
61 / 63 page Rev 1.2 / Jun. 2008 61 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP Series / H5MS1G32MFP Series POWER-UP AND INITIALIZATION SEQUENCES Mobile DDR SDRAM must be powered up and initialized in a predefined manner. Operations procedures other thank those specified may result in undefined operation. If there is any interruption to the device power, the initialization routine should be followed. The steps to be followed for device initialization are listed below. ● Step1: Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be brought up simulta- neously to prevent device latch-up. Although not required, it is recommended that VDD and VDDQ are from the same power source. Also assert and hold CLOCK ENABLE (CKE) to a LVCMOS logic high level. ● Step 2: Once the system has established consistent device power and CKE is driven high, it is safe to apply stable clock. ● Step 3: There must be at least 200us of valid clocks before any command may be given to the DRAM. During this time NOP or DESELECT commands must be issued on the command bus. ● Step 4: Issue a PRECHARGE ALL command. ● Step 5: Provide NOPs or DESELECT commands for at least tRP time. ● Step 6: Issue an AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time. Issue the second AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time. Note as part of the initialization sequence there must be two auto refresh commands issued. The typical flow is to issue them at Step 6, but they may also be issued between steps 10 and 11. ● Step 7: Using the MRS command, load the base mode register. Set the desired operating modes. ● Step 8: Provide NOPs or DESELECT commands for at least tMRD time. ● Step 9: Using the MRS command, program the extended mode register for the desired operating modes. Note the order of the base and extended mode register programming is not important. ● Step 10: Provide NOP or DESELCT commands for at least tMRD time. ● Step 11: The DRAM has been properly initialized and is ready for any valid command. |
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