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H5MS1G22MFP-E3M Datasheet(PDF) 23 Page - Hynix Semiconductor |
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H5MS1G22MFP-E3M Datasheet(HTML) 23 Page - Hynix Semiconductor |
23 / 63 page Rev 1.2 / Jun. 2008 23 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP Series / H5MS1G32MFP Series DC CHARACTERISTICS Parameter Symbol Test Condition Max Unit Note DDR 400 DDR 333 DDR 266 DDR 200 Operating one bank active-precharge current 4KBytes Page Size IDD0 tRC = tRC(min); tCK = tCK(min); CKE is HIGH; CS is HIGH between valid commands; address in- puts are SWITCHING; data bus inputs are STABLE 90 70 60 50 mA 1, 6 2KBytes Page Size 80 60 50 50 Precharge power-down standby current IDD2P all banks idle; CKE is LOW; CS is HIGH; tCK = tCK(min); address and control inputs are SWITCHING; data bus inputs are STABLE 0.4 mA Precharge power-down standby current with clock stop IDD2PS all banks idle; CKE is LOW; CS is HIGH; CK = LOW; CK = HIGH; address and control in- puts are SWITCHING; data bus inputs are STABLE 0.4 mA Precharge non power-down standby current IDD2N all banks idle; CKE is HIGH; CS is HIGH, tCK = tCK(min); address and control inputs are SWITCHING; data bus inputs are STABLE 15 12 mA Precharge non power-down standby current with clock stop IDD2NS all banks idle; CKE is HIGH; CS is HIGH; CK = LOW; CK = HIGH; address and control in- puts are SWITCHING; data bus inputs are STABLE 8 6 Active power-down standby current IDD3P one bank active; CKE is LOW; CS is HIGH; tCK = tCK(min); address and control inputs are SWITCHING; data bus inputs are STABLE 3 mA Active power-down standby current with clock stop IDD3PS one bank active; CKE is LOW; CS is HIGH; CK = LOW; CK = HIGH; address and control in- puts are SWITCHING; data bus inputs are STABLE 2 Active non power-down standby current IDD3N one bank active; CKE is HIGH; CS is HIGH; tCK = tCK(min); address and control inputs are SWITCHING; data bus inputs are STABLE 15 12 mA Active non power-down standby current with clock stop IDD3NS one bank active; CKE is HIGH; CS is HIGH; CK = LOW; CK = HIGH; address and control in- puts are SWITCHING; data bus inputs are STABLE 8 6 mA Operating burst read current IDD4R one bank active; BL=4; CL=3; tCK=tCK(min); continuous read bursts; IOUT=0mA; address in- puts are SWITCHING, 50% data change each burst transfer 150 130 110 90 mA 1 Operating burst write current IDD4W one bank active; BL=4; tCK=tCK(min); continu- ous write bursts; address inputs are SWITCHING; 50% data change each burst transfer 140 120 100 80 mA Auto Refresh Current IDD5 tRC=tRFC(min); tCK=tCK(min); burst refresh; CKE is HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 120 mA Self Refresh Current IDD6 CKE is LOW; CK=LOW; CK=HIGH; Extended Mode Register set to all 0's; address and control inputs are STABLE; data bus inputs are STABLE See Next Page uA 2 Deep Power Down Current IDD8 Address, control and data bus inputs are STABLE 10 uA 4 |
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