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H5GQ1H24AFR-T3C Datasheet(PDF) 10 Page - Hynix Semiconductor |
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H5GQ1H24AFR-T3C Datasheet(HTML) 10 Page - Hynix Semiconductor |
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10 / 173 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 10 H5GQ1H24AFR 1. INITIALIZATION 1.1. POWER‐UP SEQUENCE GDDR5 SGRAMs must be powered up and initialized in a predefined manner as shown in <Link>Figure . Operational procedures other than those specified may result in undefined operation. The Mode Registers do not have RESET default values, except for ABI#, ADR/CMD termination, and the EDC hold pattern. If the mode registers are not set dur- ing the initialization sequence, it may lead to unspecified operation. Step 1Apply power to VDD 2Apply power to VDDQ at same time or after power is applied to VDD 3Apply VREFC and VREFD at same time or after power is applied to VDDQ 4After power is stable, provide stable clock signals CK/CK# 5 Assert and hold RESET# low to ensure all drivers are in Hi‐Z and all active terminations are off. Assert and hold NOP command. 6 Wait a minimum of 200μs. 7 If boundary scan mode is necessary, SEN can be asserted HIGH to enter boundary scan mode. Boundary scan mode must be entered directly after power‐up while RESET# is low. Once boundary scan is executed, power‐up sequence should be followed. 8 Set CKE# for the desired ADR/CMD ODT settings, then bring RESET# High to latch in the logic state of CKE#, tATS and tATH must be met during this procedure. See <Link>Table 1 for the values and logic states for CKE#. The rising edge of RESET# will determine x32 mode or x16 mode depending on the state of EDC1(EDC2 when MF=1). In normal x32 mode, EDC1 has to be sustained HIGH until RESET# is HIGH. See <Link>Table for the values and logic states for EDC1(EDC2 when MF=1). 9Bring CKE# Low after tATH is satisfied 10 Wait at least 200μs referenced from the beginning of tATS 11 Issue at least 2 NOP commands 12 Issue a PRECHARGE ALL command followed by NOP commands until tRP is satisfied 13 Issue MRS command to MR15. Set GDDR5 SGRAM into address training mode (optional) 14 Complete address training (optional) 15 Issue MRS command to read the Vendor ID 16 Issue MRS command to set WCK01/WCK01# and WCK23/WCK23# termination values 17 Provide stable clock signals WCK01/WCK01# and WCK23/WCK23# 18 Issue MRS commands to use PLL or not and select the position of a WCK/CK phase detector. The use of PLL and the position of a phase detector should be issued before WCK2CK training. Issue MRS commands including PLL reset to the mode registers in any order. tMRD must be met during this procedure. WLmrs, CLmrs, CRCWL and CRCRL must be programmed before WCK2CK training. 19 Issue two REFRESH commands followed by NOP until tRFC is satisfied 20 After any necessary GDDR5 training sequences such as WCK2CK training, READ training (LDFF, RDTR) and WRITE training (WRTR, RDTR), the device is ready for operation. |
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