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H5GQ1H24AFR Datasheet(PDF) 83 Page - Hynix Semiconductor |
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H5GQ1H24AFR Datasheet(HTML) 83 Page - Hynix Semiconductor |
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83 / 173 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 83 H5GQ1H24AFR Figure 53. WSM Timing 2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK. 4. For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins. 5. Before the WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDWR must be met. DBI DBI n+7 n DO DO n+7 n DO DO m+7 m DBI DBI m+7 m Bank a, Col m Col m WL = WLmrs = 5 T7 T11 T12 T0 T1 T2 T5 T5n T6 T6n T11n T10 T10n Bank b, Col n Col n WL = WLmrs = 5 DM m 1. WLmrs = 5 and tRCDWR = 3 is shown as an example. Actual supported values will be found in the MR and AC timings sections. 3. EDC may be on or off. See Figure 4 for EDC Timing. Notes: 6. tWCK2DQI = 0 is shown for illustration purposes. DONʹT CARE TRANSITIONING DATA NOP WSM NOP WSM NOP NOP NOP NOP NOP CK CK# COMMAND ADDRESS DQ DBI# WCK# WCK ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) DM m DM m DM m DM n DM n DM n DM n |
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