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H5GQ1H24AFR Datasheet(PDF) 73 Page - Hynix Semiconductor |
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H5GQ1H24AFR Datasheet(HTML) 73 Page - Hynix Semiconductor |
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73 / 173 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 73 H5GQ1H24AFR Figure 44. Single WRITE without EDC CK CK# ADDRESS DQ DBI# WCK# WCK DO DO DBI DBI n+7 n+7 n n Bank a, Col n Col n WL = WLmrs = 3 T1 T2 T0 T3 T4 T5 T6 T7 T8 T3n T4n EDC Hold Pattern EDC 3. For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins. 4. Before the WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDWR must be met. 1. WLmrs = 3 is shown as an example. Actual supported values will be found in the MR and AC timings sections. 2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK. Notes: 5. tWCK2DQI = 0 is shown for illustration purposes. DONʹT CARE TRANSITIONING DATA NOP WRITE COMMAND NOP NOP NOP NOP NOP NOP NOP |
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